/*
 * (C) Copyright 2003
 * Texas Instruments <www.ti.com>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Alex Zuepke <azu@sysgo.de>
 *
 * (C) Copyright 2002-2004
 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
 *
 * (C) Copyright 2004
 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include "stddef.h"
#include "printf.h"
#include "2440addr.h"
#include "interrupts.h"

struct pt_regs {
    unsigned long ARM_r0;
    unsigned long ARM_r1;
    unsigned long ARM_r2;
    unsigned long ARM_r3;
    unsigned long ARM_r4;
    unsigned long ARM_r5;
    unsigned long ARM_r6;
    unsigned long ARM_r7;
    unsigned long ARM_r8;
    unsigned long ARM_r9;
    unsigned long ARM_r10;
    unsigned long ARM_fp;
    unsigned long ARM_ip;
    unsigned long ARM_sp;
    unsigned long ARM_lr;
    unsigned long ARM_pc;
    unsigned long ARM_spsr;
    unsigned long ARM_old_r0;
};

void reset_cpu(unsigned long ignored)
{
    /* Disable watchdog */
    //writel(0x0000, &watchdog->wtcon);
    rWTCON = 0x0000;

    /* Initialize watchdog timer count register */
    //writel(0x0001, &watchdog->wtcnt);
    rWTCNT = 0x0001;

    /* Enable watchdog timer; assert reset at timer timeout */
    //writel(0x0021, &watchdog->wtcon);
    rWTCON = 0x0021;

    while (1)
        /* loop forever and wait for reset to happen */;

    /*NOTREACHED*/
}
void bad_mode(void)
{
    vprintk("Resetting CPU ...\n");
    reset_cpu(0);
}
void show_regs(struct pt_regs *regs)
{
    vprintk("lr : [<%08lx>]\n"
            "sp : %08lx  ip : %08lx	 fp : %08lx\n",
            regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
    vprintk("r10: %08lx  r9 : %08lx	 r8 : %08lx\n",
            regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
    vprintk("r7 : %08lx  r6 : %08lx	 r5 : %08lx  r4 : %08lx\n",
            regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
    vprintk("r3 : %08lx  r2 : %08lx	 r1 : %08lx  r0 : %08lx\n",
            regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
}

void do_undefined_instruction(struct pt_regs *regs)
{
    vprintk("undefined instruction\n");
    show_regs(regs);
    bad_mode();
}

void do_software_interrupt(struct pt_regs *regs)
{
    vprintk("software interrupt\n");
    show_regs(regs);
    bad_mode();
}
void Swi_Bulk_Transfer_Handler(unsigned int Swi_Num)
{
    /* print swi exception number */
    switch (Swi_Num) {
        case 1:
            //vprintk("c_swi_handler:%d\t",Swi_Num);
            //Touch_Screen_Handle();
            break;

        case 2:
            vprintk("c_swi_handler:%d\t", Swi_Num);
            //Display_RTC();
            break;

        case 3:
            vprintk("c_swi_handler:%d\t", Swi_Num);
            break;
    }

    return;
}


void do_prefetch_abort(struct pt_regs *regs)
{
    vprintk("prefetch abort\n");
    show_regs(regs);
    bad_mode();
}

void do_data_abort(struct pt_regs *regs)
{
    vprintk("data abort\n");
    show_regs(regs);
    bad_mode();
}

void do_not_used(struct pt_regs *regs)
{
    vprintk("not used\n");
    show_regs(regs);
    bad_mode();
}

void arch_clear_pending_irq_bit(int bit)
{
    rSRCPND |= bit;
    rINTPND |= bit;

}

void arch_clear_pending_sub_irq_bit(int bit)
{
    rSUBSRCPND |= bit;
}

void arch_request_irq(unsigned int irq, irq_call_back call_back)
{
    unsigned int irq_table_base_addr = _ISR_STARTADDRESS + 0x20;
    unsigned int irq_table_dst_addr = irq_table_base_addr + (irq << 2);

    if (irq > IRQ_MAX) {
        vprintk("request_irq, irq > 32\n");
        return;
    }

    vprintk("request_irq, irq: %d, call_back:%p\n", irq, call_back);
    vprintk("request_irq, irq_table_base_addr: %x, irq_table_dst_addr:%x\n",
            irq_table_base_addr, irq_table_dst_addr);

    (*(unsigned int *)irq_table_dst_addr) = (unsigned int)call_back;
    enable_irq_bit(1 << irq);
}
void asm_do_IRQ(unsigned int irq)
{
    unsigned int irq_table_base_addr = _ISR_STARTADDRESS + 0x20;
    unsigned int irq_table_dst_addr = irq_table_base_addr + (irq << 2);
    irq_call_back call_back = NULL;

    if (irq > IRQ_MAX) {
        vprintk("request_irq, irq > IRQ_MAX\n");
        return;
    }

    call_back = (irq_call_back)(*(unsigned int *)irq_table_dst_addr);
    clear_pending_irq_bit(1 << irq);
    disable_irq_bit(1 << irq);
    call_back(irq);
    enable_irq_bit(1 << irq);
}

